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IEEEIAS
2009
IEEE
15 years 3 months ago
Full System Simulation and Verification Framework
In this paper, we propose a framework to develop highperformance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrat...
Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chu...
MEMOCODE
2003
IEEE
15 years 11 months ago
Bridging CSP and C++ with Selective Formalism and Executable Specifications
CSP (Communicating Sequential Processes) is a useful algebraic notation for creating a hierarchical behavioural specification for concurrent systems, due to its formal interproces...
William B. Gardner
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
16 years 6 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
ISSS
1995
IEEE
98views Hardware» more  ISSS 1995»
15 years 9 months ago
On the use of VHDL-based behavioral synthesis for telecom ASIC design
higher levels of abstraction, due to the still increasing design complexities that can be expected in the near future. Behavioral synthesis can play a key role in this prospect, as...
Mark Genoe, Paul Vanoostende, Geert van Wauwe
ICSE
2005
IEEE-ACM
16 years 6 months ago
Real-time specification patterns
Embedded systems are pervasive and frequently used for critical systems with time-dependent functionality. Dwyer et al. have developed qualitative specification patterns to facili...
Sascha Konrad, Betty H. C. Cheng