Sciweavers

788 search results - page 26 / 158
» Design and use of a system-level specification and verificat...
Sort
View
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
15 years 10 months ago
Microarchitecture Development via Metropolis Successive Platform Refinement
Productivity data for IC designs indicates an exponential increase in design time and cost with the number of elements that are to be included in a device. Present applications re...
Douglas Densmore, Sanjay Rekhi, Alberto L. Sangiov...
DAC
2006
ACM
16 years 7 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
FPL
2004
Springer
144views Hardware» more  FPL 2004»
15 years 10 months ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
DAC
2006
ACM
16 years 7 months ago
Synthesis of synchronous elastic architectures
A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automat...
Jordi Cortadella, Michael Kishinevsky, Bill Grundm...
FMSD
2002
107views more  FMSD 2002»
15 years 6 months ago
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
We present a new technique for verification of complex hardware devices that allows both generality andahighdegreeofautomation.Thetechniqueisbasedonournewwayofconstructinga"li...
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yun...