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DAC
1997
ACM
15 years 9 months ago
Formal Verification of a Superscalar Execution Unit
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
Kyle L. Nelson, Alok Jain, Randal E. Bryant
164
Voted
FM
1999
Springer
121views Formal Methods» more  FM 1999»
15 years 10 months ago
Incremental Design of a Power Transformer Station Controller Using a Controller Synthesis Methodology
ÐIn this paper, we describe the incremental specification of a power transformer station controller using a controller synthesis methodology. We specify the main requirements as s...
Hervé Marchand, Mazen Samaan
186
Voted
FDL
2004
IEEE
15 years 10 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
IEE
2008
115views more  IEE 2008»
15 years 6 months ago
Faithful mapping of model classes to mathematical structures
ion techniques are indispensable for the specification and verification of functional behavior of programs. In object-oriented ation languages like JML, a powerful abstraction tec...
Ádám Darvas, Peter Müller
DAC
2004
ACM
16 years 7 months ago
Heterogeneous MP-SoC: the solution to energy-efficient signal processing
To meet conflicting flexibility, performance and cost constraints of demanding signal processing applications, future designs in this domain will contain an increasing number of a...
Tim Kogel, Heinrich Meyr