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DAC
1999
ACM
15 years 10 months ago
Verification and Management of a Multimillion-Gate Embedded Core Design
Verification is one of the most critical and time-consuming tasks in today's design processes. This paper demonstrates the verification process of a 8.8 million gate design u...
Johann Notbauer, Thomas W. Albrecht, Georg Niedris...
DATE
2009
IEEE
109views Hardware» more  DATE 2009»
16 years 27 days ago
A design methodology for fully reconfigurable Delta-Sigma data converters
This paper presents a design methodology for fully reconfigurable low-voltage Delta-Sigma converters as for instance used in next-generation wireless applications. The design metho...
Yi Ke, Jan Craninckx, Georges G. E. Gielen
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
15 years 11 months ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar
HICSS
2007
IEEE
181views Biometrics» more  HICSS 2007»
16 years 14 days ago
A Methodology to Evaluate Agent Oriented Software Engineering Techniques
Systems using Software Agents (or Multi-Agent Systems, MAS) are becoming more popular within the development mainstream because, as the name suggests, an Agent aims to handle task...
Chia-En Lin, Krishna M. Kavi, Frederick T. Sheldon...
DSD
2002
IEEE
102views Hardware» more  DSD 2002»
15 years 11 months ago
Formal Verification of a DSP Chip Using an Iterative Approach
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
Ali Habibi, Sofiène Tahar, Adel Ghazel