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» Design and implementation of network puzzles
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DAC
2002
ACM
16 years 7 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
WWW
2007
ACM
16 years 7 months ago
Expertise networks in online communities: structure and algorithms
Web-based communities have become important places for people to seek and share expertise. We find that networks in these communities typically differ in their topology from other...
Jun Zhang, Mark S. Ackerman, Lada A. Adamic
HIPEAC
2007
Springer
16 years 20 days ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
ISMB
1996
15 years 7 months ago
Refining Neural Network Predictions for Helical Transmembrane Proteins by Dynamic Programming
For transmembrane proteins experimental determina-tion of three-dimensional structure is problematic. However, membrane proteins have important impact for molecular biology in gen...
Burkhard Rost, Rita Casadio, Piero Fariselli
HPDC
2010
IEEE
15 years 7 months ago
XCo: explicit coordination to prevent network fabric congestion in cloud computing cluster platforms
Large cluster-based cloud computing platforms increasingly use commodity Ethernet technologies, such as Gigabit Ethernet, 10GigE, and Fibre Channel over Ethernet (FCoE), for intra...
Vijay Shankar Rajanna, Smit Shah 0002, Anand Jahag...