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» Design and implementation of network puzzles
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ISPDC
2006
IEEE
16 years 19 days ago
Using Overlay Networks to Build Operating System Services for Large Scale Grids
Using grid resources to execute scientific applications requiring a large amount of computing power is attractive but not easy from the user point of view. Vigne is a grid operati...
Emmanuel Jeanvoine, Louis Rilling, Christine Morin...
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
16 years 7 days ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
16 years 7 days ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
16 years 6 days ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
DFT
2003
IEEE
132views VLSI» more  DFT 2003»
15 years 12 months ago
Level-Hybrid Optoelectronic TESH Interconnection Network
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
Vijay K. Jain, Glenn H. Chapman