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» Design and implementation of network puzzles
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ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
16 years 26 days ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
IPPS
2006
IEEE
16 years 18 days ago
The robot software communications architecture (RSCA): embedded middleware for networked service robots
In this paper, we present a robot middleware technology named Robot Software Communications Architecture (RSCA) for its use in networked home service robots. The RSCA provides a s...
Seongsoo Hong, Jaesoo Lee, Hyeonsang Eom, Gwangil ...
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
15 years 11 months ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
EUROPAR
2006
Springer
15 years 10 months ago
DOH: A Content Delivery Peer-to-Peer Network
Many SMEs and non-profit organizations suffer when their Web servers become unavailable due to flash crowd effects when their web site becomes popular. One of the solutions to the ...
Jimmy Jernberg, Vladimir Vlassov, Ali Ghodsi, Seif...