254 search results - page 21 / 51 » Design and VLSI Implementation of a Unified Synapse-Neuron A... |
172
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VLSID
2000
IEEE
15 years 9 months ago
2000
IEEE
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
156
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ISVLSI
2008
IEEE
16 years 11 days ago
2008
IEEE
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
146
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ASAP
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
172
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SBCCI
2003
ACM
15 years 11 months ago
2003
ACM
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
150
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DAC
2004
ACM
15 years 11 months ago
2004
ACM
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...