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» Design and Implementation of the NUMAchine Multiprocessor
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ICS
2010
Tsinghua U.
15 years 8 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...
ASPLOS
2008
ACM
15 years 8 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
IPPS
2009
IEEE
16 years 21 days ago
Scalable RDMA performance in PGAS languages
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
Montse Farreras, George Almási, Calin Casca...
CODES
2008
IEEE
16 years 15 days ago
A security monitoring service for NoCs
As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-onChip (...
Leandro Fiorin, Gianluca Palermo, Cristina Silvano
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
16 years 3 days ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...