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DATE
2008
IEEE
91views Hardware» more  DATE 2008»
16 years 1 months ago
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation
Transaction Level Modeling (TLM) is an emerging design practice for overcoming increasing design complexity. It aims at simplifying the design flow of embedded systems ning and v...
Nicola Bombieri, Nicola Deganello, Franco Fummi
ISLPED
2003
ACM
80views Hardware» more  ISLPED 2003»
15 years 12 months ago
Level conversion for dual-supply systems
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic
CORR
2012
Springer
212views Education» more  CORR 2012»
14 years 2 months ago
A Bi-Directional Refinement Algorithm for the Calculus of (Co)Inductive Constructions
The paper describes the refinement algorithm for the Calculus of (Co)Inductive Constructions (CIC) implemented in the interactive theorem prover Matita. The refinement algorithm ...
Andrea Asperti, Wilmer Ricciotti, Claudio Sacerdot...
CODES
1996
IEEE
15 years 10 months ago
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
The TaSCA environment for hardware/software co-design of control dominated systems implemented on a single chip includes a novel approach to the system exploration phase for the e...
Alessandro Balboni, William Fornaciari, Donatella ...
IPPS
2008
IEEE
16 years 1 months ago
Design of scalable dense linear algebra libraries for multithreaded architectures: the LU factorization
The scalable parallel implementation, targeting SMP and/or multicore architectures, of dense linear algebra libraries is analyzed. Using the LU factorization as a case study, it is...
Gregorio Quintana-Ortí, Enrique S. Quintana...