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DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 11 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
COMSWARE
2006
IEEE
15 years 10 months ago
Architecting protocol stack optimizations on mobile devices
Applications using traditional protocol stacks (e.g TCP/IP) from wired networks do not function efficiently in mobile wireless scenarios. This is primarily due to the layered archi...
Vijay T. Raisinghani, Sridhar Iyer
SPLC
2000
15 years 7 months ago
Two Novel Concepts for systematic product line development
: Framelets and implementation cases are new concepts to manage the complexity of product line development. Framelets are "small product lines" that address, as self-stan...
Alessandro Pasetti, Wolfgang Pree
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
15 years 11 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
DAC
2007
ACM
16 years 7 months ago
Self-Resetting Latches for Asynchronous Micro-Pipelines
Asynchronous circuits are increasingly attractive as low power or high-performance replacements to synchronous designs. A key part of these circuits are asynchronous micropipeline...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...