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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
16 years 4 days ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
15 years 11 months ago
Energy/Power Estimation of Regular Processor Arrays
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
Sanjay V. Rajopadhye, Steven Derrien
FPLE
1995
15 years 10 months ago
Compiler Construction Using Scheme
This paper describes a course in compiler design that focuses on the Scheme implementation of a Scheme compiler that generates native assembly code for a real architecture. The co...
Eric Hilsdale, J. Michael Ashley, R. Kent Dybvig, ...
EMSOFT
2004
Springer
16 years 8 days ago
Exploiting prescriptive aspects: a design time capability
Aspect oriented programming (AOP), when used well, has many advantages. Aspects are however, programming-time constructs, i.e., they relate to source code. Previously, we develope...
John A. Stankovic, Prashant Nagaraddi, Zhendong Yu...
ENTCS
2006
163views more  ENTCS 2006»
15 years 6 months ago
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchr...
Frank K. Gürkaynak, Stephan Oetiker, Hubert K...