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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
16 years 3 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue
DATE
2003
IEEE
93views Hardware» more  DATE 2003»
15 years 12 months ago
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
Edwin Rijpkema, Kees G. W. Goossens, Andrei Radule...
IWPC
2003
IEEE
15 years 12 months ago
Design Recovery of a Two Level System
Many applications have one or more important modules that are written in a language other than conventional procedural or object oriented languages. These languages are often tran...
Thomas R. Dean, Yuling Chen
IJCNN
2000
IEEE
15 years 11 months ago
Design and Evaluation of Neural Networks for Coin Recognition by Using GA and SA
In this paper, we propose a method to design a neural network(NN) by using a genetic algorithm(GA) and simulated annealing(SA). And also, in order to demonstrate the effectivenes...
Yasue Mitsukura, Minoru Fukumi, Norio Akamatsu
IPPS
1998
IEEE
15 years 11 months ago
PULC: ParaStation User-Level Communication. Design and Overview
PULC is a user-level communication library for workstation clusters. PULC provides a multi-user, multi-programming communication library for user level communication on top of high...
Joachim M. Blum, Thomas M. Warschko, Walter F. Tic...