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ISPD
2005
ACM
140views Hardware» more  ISPD 2005»
16 years 22 days ago
Are floorplan representations important in digital design?
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
IOLTS
2009
IEEE
231views Hardware» more  IOLTS 2009»
16 years 1 months ago
Designing fault tolerant FSM by nano-PLA
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault toleran...
Samary Baranov, Ilya Levin, Osnat Keren, Mark G. K...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
16 years 1 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
VLSI
2005
Springer
16 years 19 days ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
CAISE
2004
Springer
16 years 17 days ago
Towards Computer-aided Design of OCL Constraints
In UML2.0, significant efforts have been devoted towards a better definition of OCL. Still, the adoption of the language by the software engineers remains a significant challenge....
Yves Ledru, Sophie Dupuy-Chessa, Hind Fadil