Sciweavers

605 search results - page 53 / 121
» Design Principles for Combiners with Memory
Sort
View
ICPP
2005
IEEE
15 years 11 months ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...
ICPP
2003
IEEE
15 years 11 months ago
Hardware-Assisted Design for Fast Packet Forwarding in Parallel Routers
A hardware-assisted design, dubbed cache-oriented multistage structure (COMS), is proposed for fast packet forwarding. COMS incorporates small on-chip cache memory in its constitu...
Nian-Feng Tzeng
ANCS
2009
ACM
15 years 3 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
16 years 6 months ago
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips
Recent advances in microfluidics technology have led to the emergence of miniaturized biochip devices for biochemical analysis. A promising category of microfluidic biochips relie...
Tao Xu, Krishnendu Chakrabarty, Fei Su
AIED
2005
Springer
15 years 11 months ago
Serious Games for Language Learning: How Much Game, How Much AI?
Modern computer games show potential not just for engaging and entertaining users, but also in promoting learning. Game designers employ a range of techniques to promote long-term ...
W. Lewis Johnson, Hannes Högni Vilhjál...