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HPCA
2000
IEEE
15 years 11 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
WWW
2006
ACM
16 years 7 months ago
DoNet: a semantic domotic framework
In the very near future complete households will be entirely networked as a de facto standard. In this poster we briefly describe our work in the area of domotics, where personali...
Malcolm Attard, Matthew Montebello
ICCD
2004
IEEE
126views Hardware» more  ICCD 2004»
16 years 3 months ago
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
Joshua L. Kihm, Daniel A. Connors
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
16 years 1 months ago
A highly resilient routing algorithm for fault-tolerant NoCs
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will so...
David Fick, Andrew DeOrio, Gregory K. Chen, Valeri...
WMCSA
2009
IEEE
16 years 1 months ago
BALANCE: towards a usable pervasive wellness application with accurate activity inference
Technology offers the potential to objectively monitor people‘s eating and activity behaviors and encourage healthier lifestyles. BALANCE is a mobile phone-based system for long...
Tamara Denning, Adrienne H. Andrew, Rohit Chaudhri...