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MM
2004
ACM
107views Multimedia» more  MM 2004»
15 years 12 months ago
Time, voice, and joyce
We present a design for recapitulating walks through Dublin's City Centre by characters in James Joyce's Ulysses. Our computationally supported walkers will avail themse...
Andrea Taylor, Brendan Donovan, Zoltan Foley-Fishe...
DAC
2008
ACM
16 years 7 months ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
ISMAR
2002
IEEE
15 years 11 months ago
Augmented Urban Planning Workbench: Overlaying Drawings, Physical Models and Digital Simulation
There is a problem in the spatial and temporal separation between the varying forms of representation used in urban design. Sketches, physical models, and more recently computatio...
Hiroshi Ishii, Eran Ben-Joseph, John Underkoffler,...
ICCAD
1996
IEEE
133views Hardware» more  ICCAD 1996»
15 years 10 months ago
Basic concepts for an HDL reverse engineering tool-set
Designer's productivity has become the key-factor of the development of electronic systems. An increasing application of design data reuse is widely recognized as a promising...
Gunther Lehmann, Bernhard Wunder, Klaus D. Mü...
TPDS
2002
105views more  TPDS 2002»
15 years 6 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills