473 search results - page 8 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
139
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GLVLSI
2006
IEEE
15 years 12 months ago
2006
IEEE
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
144
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ICCD
2004
IEEE
16 years 2 months ago
2004
IEEE
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
140
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
165
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
151
Voted
ISCAS
2002
IEEE
2002
IEEE
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
15 years 11 months ago
A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a ...