473 search results - page 47 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
164
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CF
2004
ACM
15 years 11 months ago
2004
ACM
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
178
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DAC
2004
ACM
15 years 9 months ago
2004
ACM
A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an effic...
150
Voted
ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
186
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VTS
2000
IEEE
15 years 10 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
171
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ASPDAC
2004
ACM
15 years 11 months ago
2004
ACM
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...