473 search results - page 40 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
183
click to vote
DAC
2006
ACM
16 years 7 months ago
2006
ACM
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
165
click to vote
GLVLSI
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
127
click to vote
DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
— We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking problem) — a key step in incremental logic design that identif...
182
click to vote
GECCO
2004
Springer
15 years 11 months ago
2004
Springer
This article summarizes two experiments utilizing building blocks to find analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 pr...
181
click to vote
DGO
2007
15 years 7 months ago
2007
A large portion of the government, business, cultural, and scientific digital data being created today needs to be archived and preserved for future use of periods ranging from a ...