473 search results - page 27 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
169
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
151
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SBCCI
2006
ACM
15 years 12 months ago
2006
ACM
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
145
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DATE
2009
IEEE
16 years 23 days ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
120
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DATE
2008
IEEE
16 years 14 days ago
2008
IEEE
This paper presents the design and the laboratory results of an integrated half-bridge driver for power electronic systems in a 0.35 µm Bipolar CMOS DMOS (BCD) technology. The pr...
159
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ICCAD
2007
IEEE
16 years 2 months ago
2007
IEEE
— We introduce a remote activation scheme that aims to protect integrated circuits (IC) intellectual property (IP) against piracy. Remote activation enables designers to lock eac...