473 search results - page 22 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
164
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ISQED
2000
IEEE
2000
IEEE
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
15 years 10 months ago
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
166
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ISQED
2009
IEEE
16 years 24 days ago
2009
IEEE
Active decoupling capacitors (decaps) are more effective than passive decaps at reducing local IR-drop problems in the power distribution network. In the basic active decap, two p...
130
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GLVLSI
2006
IEEE
16 years 1 days ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
170
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TVLSI
2008
15 years 5 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
153
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ICCAD
2001
IEEE
16 years 2 months ago
2001
IEEE
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...