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DAC
2003
ACM
15 years 12 months ago
Realizable RLCK circuit crunching
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...
EVOW
2001
Springer
15 years 11 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
AMOST
2007
ACM
15 years 10 months ago
Achieving both model and code coverage with automated gray-box testing
We have devised a novel technique to automatically generate test cases for a software system, combining black-box model-based testing with white-box parameterized unit testing. Th...
Nicolas Kicillof, Wolfgang Grieskamp, Nikolai Till...
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
15 years 10 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
ICSE
2007
IEEE-ACM
16 years 6 months ago
Ownership and Immutability Inference for UML-Based Object Access Control
We propose a mechanism for object access control which is based on the UML. Specifically, we propose use of ownership and immutability constraints on UML associations and verifica...
Yin Liu, Ana Milanova