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ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
15 years 10 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
CONCURRENCY
2004
151views more  CONCURRENCY 2004»
15 years 6 months ago
User transparency: a fully sequential programming model for efficient data parallel image processing
Although many image processing applications are ideally suited for parallel implementation, most researchers in imaging do not benefit from high performance computing on a daily b...
Frank J. Seinstra, Dennis Koelma
EURODAC
1995
IEEE
156views VHDL» more  EURODAC 1995»
15 years 10 months ago
VHDL quality: synthesizability, complexity and efficiency evaluation
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
M. Mastretti
IS
2010
15 years 5 months ago
Evaluating ontologies: Towards a cognitive measure of quality
Business process models are an important tool in understanding and improving the efficiency of a business and in the design of information systems. Recent work has evaluated busin...
Joerg Evermann, Jennifer Fang
CHI
2007
ACM
16 years 6 months ago
ExperiScope: an analysis tool for interaction data
We present ExperiScope, an analytical tool to help designers and experimenters explore the results of quantitative evaluations of interaction techniques. ExperiScope combines a ne...
François Guimbretière, Ken Hinckley,...