The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...
In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 ...
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
In high energy physics, bioinformatics, and other disciplines, we encounter applications involving numerous, loosely coupled jobs that both access and generate large data sets. So...
Abstract. We provide a framework for the design and analysis of dynamic programming algorithms for surface-embedded graphs on n vertices and branchwidth at most k. Our technique ap...
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...