Sciweavers

3280 search results - page 270 / 656
» Design Families and Design Individuals
Sort
View
ICCD
1995
IEEE
83views Hardware» more  ICCD 1995»
15 years 10 months ago
Concurrent timing optimization of latch-based digital systems
Many design techniques have been proposed to optimize the performance of a digital system implemented in a given technology. Each of these techniques can be advantageous in partic...
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C...
DATE
2010
IEEE
147views Hardware» more  DATE 2010»
15 years 9 months ago
Detecting/preventing information leakage on the memory bus due to malicious hardware
An increasing concern amongst designers and integrators of military and defense-related systems is the underlying security of the individual microprocessor components that make up ...
Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok ...
ACMACE
2005
ACM
15 years 8 months ago
Interactive and enjoyable interface in museum
Exhibitions at a scientific museum are usually difficult for ordinary school pupils. To improve the issues of current explanation systems, we use Personal Data Assistant (PDA) dev...
Fusako Kusunoki, Takako Yamaguti, Takuichi Nishimu...
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Yan Lin, Fei Li, Lei He
CEC
2007
IEEE
15 years 8 months ago
Fitness inheritance in evolutionary and multi-objective high-level synthesis
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
Christian Pilato, Gianluca Palermo, Antonino Tumeo...