Sciweavers

3280 search results - page 245 / 656
» Design Families and Design Individuals
Sort
View
DAC
2007
ACM
16 years 7 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
16 years 3 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
ISAAC
2009
Springer
114views Algorithms» more  ISAAC 2009»
16 years 1 months ago
Good Programming in Transactional Memory
Abstract. In a multicore transactional memory (TM) system, concurrent execution threads interact and interfere with each other through shared memory. The less interference a progra...
Raphael Eidenbenz, Roger Wattenhofer
AGILEDC
2008
IEEE
16 years 1 months ago
Utilizing Digital Tabletops in Collocated Agile Planning Meetings
In agile software development, planning meetings play a pivotal role in establishing a concrete understanding of customers’ requirements. Using tools to enhance the effectivenes...
Yaser Ghanam, Xin Wang, Frank Maurer
HICSS
2002
IEEE
128views Biometrics» more  HICSS 2002»
15 years 11 months ago
Flexible Instructional Strategies for E-learning
This paper provides an overview on a German lighthouse research project called L3 in the area of e-learning systems that supply e-learning services via a virtual private network. ...
Michael Altenhofen, Joachim Schaper