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ICCAD
1998
IEEE
71views Hardware» more  ICCAD 1998»
15 years 11 months ago
High-level variable selection for partial-scan implementation
In this paper, we propose a high-level variable selection for partial-scan approach to improve the testability of digital systems. The testability of a design is evaluated at the ...
Frank F. Hsu, Janak H. Patel
DAC
1994
ACM
15 years 10 months ago
A Modular Partitioning Approach for Asynchronous Circuit Synthesis
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
Ruchir Puri, Jun Gu
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
DAC
2008
ACM
15 years 8 months ago
Analog parallelism in ring-based VCOs
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
Daeik D. Kim, Choongyeun Cho, Jonghae Kim
IGARSS
2010
15 years 4 months ago
Realization of the NASA Dual-Frequency Dual-Polarized Doppler Radar (D3R)
This paper describes some of the novel technologies adopted in the realization of the NASA Dual-frequency Dualpolarized Doppler Radar (D3R) system for to be used by the GPM ground...
Manuel Vega, James Carswell, V. Chandrasekar, Math...