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TASLP
2010
99views more  TASLP 2010»
15 years 5 months ago
A Virtual Model of Spring Reverberation
—The digital emulation of analog audio effects and synthesis components, through the simulation of lumped circuit components has seen a large amount of activity in recent years; ...
Stefan Bilbao, Julian Parker
ARCS
2009
Springer
16 years 1 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
SOSP
2007
ACM
16 years 3 months ago
Attested append-only memory: making adversaries stick to their word
Researchers have made great strides in improving the fault tolerance of both centralized and replicated systems against arbitrary (Byzantine) faults. However, there are hard limit...
Byung-Gon Chun, Petros Maniatis, Scott Shenker, Jo...
CODES
2001
IEEE
15 years 10 months ago
A practical tool box for system level communication synthesis
This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on ...
Denis Hommais, Frédéric Pétro...
FPT
2005
IEEE
198views Hardware» more  FPT 2005»
16 years 17 days ago
From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
Wolfgang Klingauf, Robert Günzel