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CP
2009
Springer
16 years 7 months ago
Generating Optimal Stowage Plans for Container Vessel Bays
Millions of containers are stowed every week with goods worth billions of dollars, but container vessel stowage is an all but neglected combinatorial optimization problem. In this ...
Alberto Delgado, Christian Schulte, Rune Mø...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
WSC
2007
15 years 8 months ago
Modeling and simulation for customer driven manufacturing system design and operations planning
Agility, speed and flexibility in production networks are required in today's global competition in the flat world. The accuracy of order date delivery promises is a key elem...
Juhani Heilala, Jari Montonen, Arttu Salmela, Pasi...
ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
14 years 2 months ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
ICFP
2005
ACM
16 years 6 months ago
A logical analysis of aliasing in imperative higher-order functions
We present a compositional program logic for call-by-value imperative higher-order functions with general forms of aliasing, which can arise from the use of reference names as fun...
Martin Berger, Kohei Honda, Nobuko Yoshida