A multiprocessor prefetch scheme is described in which a miss is followed by a prefetch of a group of lines, a neighborhood, surrounding the demand-fetched line. The neighborhood ...
Abstract— In this paper, we share our experience in designing and building a content based switch which we call L5. In addition to the layer 2-3-4 information available in the pa...
George Apostolopoulos, David Aubespin, Vinod G. J....
— This paper describes the design and implementation of a protocol scrubber, a transparent interposition mechanism for explicitly removing network attacks at both the transport a...
G. Robert Malan, David Watson, Farnam Jahanian, Pa...
We describe MGV, an integrated visualization and exploration system for massive multi-digraph navigation. MGV’s only assumption is that the vertex set of the underlying digraph ...
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...
Jason Hiser, Steve Carr, Philip H. Sweany, Steven ...