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MICRO
2003
IEEE
132views Hardware» more  MICRO 2003»
15 years 12 months ago
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasa...
DAC
1996
ACM
15 years 10 months ago
Optimal Clock Skew Scheduling Tolerant to Process Variations
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
José Luis Neves, Eby G. Friedman
ICMLA
2007
15 years 8 months ago
Understanding Challenges in Preserving and Reconstructing Computer-Assisted Medical Decision Processes
— This paper addresses the problem of understanding preservation and reconstruction requirements for computeraided medical decision-making. With an increasing number of computer-...
Sang-Chul Lee, Peter Bajcsy
VLSISP
2008
104views more  VLSISP 2008»
15 years 6 months ago
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array ele...
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verd...
HPCA
2012
IEEE
14 years 2 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...