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ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
16 years 3 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
WCNC
2008
IEEE
16 years 15 days ago
Adaptive Tuning of MIMO-Enabled 802.11e WLANs with Network Utility Maximization
— The IEEE 802.11-based wireless local area networks (WLANs) are widely used for high-speed wireless data access. With the recent 802.11e quality-of-service (QoS) extension, real...
Yuxia Lin, Vincent W. S. Wong
JEC
2006
71views more  JEC 2006»
15 years 6 months ago
Destructive-read in embedded DRAM, impact on power consumption
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Gran...
SIMPRA
2011
15 years 1 months ago
A real-time multigrid finite hexahedra method for elasticity simulation using CUDA
In this paper we present a GPU-based multigrid approach for simulating elastic deformable objects in real time. Our method is based on a finite element discretization of the defo...
Christian Dick, Joachim Georgii, Rüdiger West...
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
14 years 9 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross