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ICPADS
2006
IEEE
16 years 27 days ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
IEEEPACT
2006
IEEE
16 years 27 days ago
A two-phase escape analysis for parallel java programs
Thread escape analysis conservatively determines which objects may be accessed in more than one thread. Thread escape analysis is useful for a variety of purposes – finding rac...
Kyungwoo Lee, Samuel P. Midkiff
IEEEPACT
2006
IEEE
16 years 27 days ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
IJCNN
2006
IEEE
16 years 27 days ago
A Monte Carlo Sequential Estimation for Point Process Optimum Filtering
— Adaptive filtering is normally utilized to estimate system states or outputs from continuous valued observations, and it is of limited use when the observations are discrete e...
Yiwen Wang 0002, António R. C. Paiva, Jose ...
INFOCOM
2006
IEEE
16 years 26 days ago
DDoS-Resilient Scheduling to Counter Application Layer Attacks Under Imperfect Detection
— Countering Distributed Denial of Service (DDoS) attacks is becoming ever more challenging with the vast resources and techniques increasingly available to attackers. In this pa...
Supranamaya Ranjan, Ram Swaminathan, Mustafa Uysal...
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