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RTAS
2006
IEEE
16 years 18 days ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
SRDS
2006
IEEE
16 years 18 days ago
Reliably Executing Tasks in the Presence of Untrusted Entities
In this work we consider a distributed system formed by a master processor and a collection of n processors (workers) that can execute tasks; worker processors are untrusted and m...
Antonio Fernández, Luis López, Agust...
ASPLOS
2006
ACM
16 years 17 days ago
Tradeoffs in transactional memory virtualization
For transactional memory (TM) to achieve widespread acceptance, transactions should not be limited to the physical resources of any specific hardware implementation. TM systems s...
JaeWoong Chung, Chi Cao Minh, Austen McDonald, Tra...
HRI
2006
ACM
16 years 17 days ago
Interaction debugging: an integral approach to analyze human-robot interaction
Along with the development of interactive robots, controlled experiments and field trials are regularly conducted to stage human-robot interaction. Experience in this field has sh...
Tijn Kooijmans, Takayuki Kanda, Christoph Bartneck...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
16 years 16 days ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
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