4245 search results - page 749 / 849 » Delay Tolerant Networking |
159
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SLIP
2003
ACM
15 years 11 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
170
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DSN
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
178
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LCN
2002
IEEE
15 years 11 months ago
2002
IEEE
Parallel Packet Switches (PPS) use internal, parallel switch planes that operate at less than line speed. A PPS can scale-up to faster line speeds than a single-plane switch can. ...
182
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CLUSTER
2000
IEEE
15 years 10 months ago
2000
IEEE
To construct a large commodity clustec a hierarchical network is generally adopted for connecting the host muchines, where a Gigabit backbone switch connects a few commodity switc...
174
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ICNP
1998
IEEE
15 years 10 months ago
1998
IEEE
To construct high performance Web servers, system builders are increasingly turning to distributed designs. An important challenge that arises in such designs is the need to direc...