4245 search results - page 356 / 849 » Delay Tolerant Networking |
166
click to vote
DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
169
click to vote
MICRO
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
140
click to vote
GLVLSI
2000
IEEE
15 years 11 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
184
click to vote
HPCA
1999
IEEE
15 years 11 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
164
click to vote
ICCAD
1999
IEEE
15 years 11 months ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...