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134
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DATE
2009
IEEE
86views Hardware» more  DATE 2009»
16 years 1 months ago
A power-efficient migration mechanism for D-NUCA caches
D-NUCA L2 caches are able to tolerate the increasing wire delay effects due to technology scaling thanks to their banked organization, broadcast line search and data promotion/dem...
Alessandro Bardine, Manuel Comparetti, Pierfrances...
ASYNC
2007
IEEE
131views Hardware» more  ASYNC 2007»
16 years 1 months ago
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia...
ICPPW
2006
IEEE
16 years 21 days ago
Model Checking Control Communication of a FACTS Device
This paper concerns the design and verification of a realtime communication protocol for sensor data collection and processing between an embedded computer and a DSP. In such sys...
David A. Cape, Bruce M. McMillin, James K. Townsen...
ISLPED
2006
ACM
129views Hardware» more  ISLPED 2006»
16 years 18 days ago
Variation-driven device sizing for minimum energy sub-threshold circuits
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
Joyce Kwong, Anantha P. Chandrakasan
ATS
2005
IEEE
104views Hardware» more  ATS 2005»
16 years 8 days ago
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM
In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell...
Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Ma...