4245 search results - page 267 / 849 » Delay Tolerant Networking |
143
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FPL
2007
Springer
16 years 25 days ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
169
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ISCAS
2005
IEEE
16 years 7 days ago
2005
IEEE
— This paper considers the application of the neural networks for the guaranteed cost control problem of discrete– time uncertain systems that have in both state and input dela...
180
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INFOCOM
2000
IEEE
15 years 11 months ago
2000
IEEE
— The packet losses imposed by IP networks can cause long and erratic recovery delays, since senders must often use conservative loss detection and retransmission mechanisms. Thi...
170
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FPGA
1998
ACM
15 years 11 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
209
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INFOCOM
1993
IEEE
15 years 10 months ago
1993
IEEE
We propose a new service discipline, called the RateControlledStatic-Priority (RCSP) queueingdiscipline, that can provide throughput, delay, delay jitter, and loss free guarantees...