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DFT
2005
IEEE
178views VLSI» more  DFT 2005»
16 years 4 days ago
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
ARVLSI
1995
IEEE
78views VLSI» more  ARVLSI 1995»
15 years 10 months ago
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Sch...
SOSP
2001
ACM
16 years 3 months ago
BASE: Using Abstraction to Improve Fault Tolerance
ing Abstraction to Improve Fault Tolerance MIGUEL CASTRO Microsoft Research and RODRIGO RODRIGUES and BARBARA LISKOV MIT Laboratory for Computer Science Software errors are a major...
Rodrigo Rodrigues, Miguel Castro, Barbara Liskov
COMPSAC
1998
IEEE
15 years 10 months ago
Architecture of ROAFTS/Solaris: A Solaris-Based Middleware for Real-Time Object-Oriented Adaptive Fault Tolerance Support
Middleware implementation of various critical services required by large-scale and complex real-time applications on top of COTS operating system is currently an approach of growi...
Eltefaat Shokri, Patrick Crane, K. H. Kim, Chittur...
ICIP
2000
IEEE
16 years 8 months ago
Compression Tolerant Watermarking for Image Verification
Digital Watermarking is seen as a viable solution to authentication of multimedia data and hence its security, especially in a networked environment. In this paper we present a ne...
Harpal S. Bassali, Jatin Chhugani, Saurabh Agarwal...