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DSN
2008
IEEE
15 years 8 months ago
Detouring: Translating software to circumvent hard faults in simple cores
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...
Albert Meixner, Daniel J. Sorin
DSN
2007
IEEE
16 years 24 days ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
DSN
2007
IEEE
15 years 10 months ago
Determining Fault Tolerance of XOR-Based Erasure Codes Efficiently
We propose a new fault tolerance metric for XOR-based erasure codes: the minimal erasures list (MEL). A minimal erasure is a set of erasures that leads to irrecoverable data loss ...
Jay J. Wylie, Ram Swaminathan
IPPS
1996
IEEE
15 years 10 months ago
Partitionability of the Multistage Interconnection Networks
- Partitionability allows the creation of many physically independent subsystems, each of which retains an identical functionality as its parent network and has no communication in...
Yeimkuan Chang
ICONIP
2008
15 years 8 months ago
On Node-Fault-Injection Training of an RBF Network
Abstract. While injecting fault during training has long been demonstrated as an effective method to improve fault tolerance of a neural network, not much theoretical work has been...
John Sum, Chi-Sing Leung, Kevin Ho