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DATE
2004
IEEE
116views Hardware» more  DATE 2004»
15 years 10 months ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
16 years 1 months ago
Trace signal selection for visibility enhancement in post-silicon validation
Today’s complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from presilicon verification. One effective silicon debug ...
Xiao Liu, Qiang Xu
DATE
2009
IEEE
79views Hardware» more  DATE 2009»
16 years 1 months ago
Solver technology for system-level to RTL equivalence checking
—Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, ...
Alfred Kölbl, Reily Jacoby, Himanshu Jain, Ca...
DATE
2009
IEEE
151views Hardware» more  DATE 2009»
16 years 1 months ago
Combined system synthesis and communication architecture exploration for MPSoCs
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
Martin Lukasiewycz, Martin Streubühr, Michael...
DATE
2009
IEEE
194views Hardware» more  DATE 2009»
16 years 1 months ago
A UML frontend for IP-XACT-based IP management
—IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these description...
Tim Schattkowsky, Tao Xie, Wolfgang Mueller