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DATE
2006
IEEE
135views Hardware» more  DATE 2006»
16 years 21 days ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
DATE
2006
IEEE
90views Hardware» more  DATE 2006»
16 years 21 days ago
Microarchitectural floorplanning under performance and thermal tradeoff
— In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design ...
Michael B. Healy, Mario Vittes, Mongkol Ekpanyapon...
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
16 years 21 days ago
A methodology for FPGA to structured-ASIC synthesis and verification
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...
DATE
2005
IEEE
125views Hardware» more  DATE 2005»
16 years 8 days ago
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler
Embedded software continues to play an ever increasing role in the design of complex embedded applications. In part, the elevel of abstraction provided by a high-level programming...
André C. Nácul, Tony Givargis
DATE
2003
IEEE
135views Hardware» more  DATE 2003»
15 years 12 months ago
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristic...
Nicola Drago, Franco Fummi, Marco Monguzzi, Giovan...