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IEEEPACT
2008
IEEE
16 years 23 days ago
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
Katherine E. Coons, Behnam Robatmili, Matthew E. T...
IISWC
2008
IEEE
16 years 23 days ago
STAMP: Stanford Transactional Applications for Multi-Processing
Abstract—Transactional Memory (TM) is emerging as a promising technology to simplify parallel programming. While several TM systems have been proposed in the research literature,...
Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, ...
IJCNN
2008
IEEE
16 years 23 days ago
Filter Bank Common Spatial Pattern (FBCSP) in Brain-Computer Interface
—In motor imagery-based Brain Computer Interfaces (BCI), discriminative patterns can be extracted from the electroencephalogram (EEG) using the Common Spatial Pattern (CSP) algor...
Kai Keng Ang, Zhang Yang Chin, Haihong Zhang, Cunt...
ISCA
2008
IEEE
134views Hardware» more  ISCA 2008»
16 years 23 days ago
Flexible Decoupled Transactional Memory Support
A high-concurrency transactional memory (TM) implementation needs to track concurrent accesses, buffer speculative updates, and manage conflicts. We present a system, FlexTM (FLE...
Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. ...
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
16 years 22 days ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
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