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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
16 years 24 days ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
VTC
2007
IEEE
161views Communications» more  VTC 2007»
16 years 24 days ago
Early Results on Hydra: A Flexible MAC/PHY Multihop Testbed
— Hydra is a flexible wireless network testbed being developed at UT Austin. Our focus is networks that support multiple wireless hops and where the network, especially the MAC,...
Ketan Mandke, Soon-Hyeok Choi, Gibeom Kim, Robert ...
CAV
2007
Springer
108views Hardware» more  CAV 2007»
16 years 21 days ago
Systematic Acceleration in Regular Model Checking
Abstract. Regular model checking is a form of symbolic model checking technique for systems whose states can be represented as finite words over a finite alphabet, where regular ...
Bengt Jonsson, Mayank Saksena
CHES
2007
Springer
327views Cryptology» more  CHES 2007»
16 years 21 days ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima
EMSOFT
2007
Springer
16 years 21 days ago
Methods for multi-dimensional robustness optimization in complex embedded systems
Design space exploration of embedded systems typically focuses on classical design goals such as cost, timing, buffer sizes, and power consumption. Robustness criteria, i.e. sensi...
Arne Hamann, Razvan Racu, Rolf Ernst
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