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154
Voted
ITC
2003
IEEE
176views Hardware» more  ITC 2003»
16 years 2 days ago
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
Olivier Caty, Ismet Bayraktaroglu, Amitava Majumda...
LCN
2003
IEEE
16 years 2 days ago
Evaluating System Performance in Gigabit Networks
- With the current wide deployment of Gigabit Ethernet technology in the backbone and workgroup switches, the network performance bottleneck has shifted for the first time in nearl...
Khaled Salah, K. El-Badawi
MSS
2003
IEEE
83views Hardware» more  MSS 2003»
16 years 2 days ago
Reliability Mechanisms for Very Large Storage Systems
Reliability and availability are increasingly important in large-scale storage systems built from thousands of individual storage devices. Large systems must survive the failure o...
Qin Xin, Ethan L. Miller, Thomas J. E. Schwarz, Da...
167
Voted
SP
2003
IEEE
16 years 2 days ago
Using Memory Errors to Attack a Virtual Machine
We present an experimental study showing that soft memory errors can lead to serious security vulnerabilities in Java and .NET virtual machines, or in any system that relies on ty...
Sudhakar Govindavajhala, Andrew W. Appel
VISUALIZATION
2003
IEEE
16 years 2 days ago
Visualizing Spatial and Temporal Variability in Coastal Observatories
In this paper, we describe a set of 3D and 4D visualization tools and techniques for CORIE, a complex environmental observation and forecasting system (EOFS) for the Columbia Rive...
Walter Jiménez, Wagner Toledo Corrêa,...
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