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168
Voted
IPPS
2006
IEEE
16 years 27 days ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
206
Voted
IPPS
2006
IEEE
16 years 27 days ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
198
Voted
IROS
2006
IEEE
16 years 27 days ago
2006
IEEE
— This paper presents a self-localization strategy for a team of heterogenous mobile robots, including ground mobile robots of various sizes and wall-climbing robots. These robot...
157
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ISCA
2006
IEEE
16 years 27 days ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
191
Voted
ISPASS
2006
IEEE
16 years 26 days ago
2006
IEEE
SimPoint is a technique used to pick what parts of the program’s execution to simulate in order to have a complete picture of execution. SimPoint uses data clustering algorithms...