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» Data Dependent Circuit Design: A Case Study
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VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
16 years 6 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
CSREAESA
2004
15 years 7 months ago
A High Performance, Low Area Overhead Carry Lookahead Adder
Adders are some of the most critical data path circuits requiring considerable design effort in order to "squeeze" out as much performance gain as possible. Many adder d...
James Levy, Jabulani Nyathi
KBSE
2008
IEEE
16 years 20 days ago
Exploring the composition of unit test suites
In agile software development, test code can considerably contribute to the overall source code size. Being a valuable asset both in terms of verification and documentation, the ...
Bart Van Rompaey, Serge Demeyer
CSE
2009
IEEE
16 years 1 months ago
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...
Sebastian Hessel, David Szczesny, Shadi Traboulsi,...
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
15 years 10 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey