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» DPS - Dynamic Parallel Schedules
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IPPS
2003
IEEE
15 years 11 months ago
Performance Modeling for Entity-Level Simulations
Advances across many fields of study are driving changes in the basic nature of scientific computing applications. Scientists have recognized a growing need to study phenomena b...
Alan Su, Francine Berman, Henri Casanova
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 11 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
ICPPW
2002
IEEE
15 years 11 months ago
MigThread: Thread Migration in DSM Systems
Distributed Shared Memory (DSM) systems provide a logically shared memory over physically distributed memory to enable parallel computation on Networks of Workstations (NOWs). In ...
Hai Jiang, Vipin Chaudhary
LCPC
2001
Springer
15 years 10 months ago
Bridging the Gap between Compilation and Synthesis in the DEFACTO System
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoun...
IEEEPACT
2000
IEEE
15 years 10 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier