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CHES
2006
Springer
124views Cryptology» more  CHES 2006»
15 years 10 months ago
A Proposition for Correlation Power Analysis Enhancement
Cryptographic devices are vulnerable to the nowadays well known side channel leakage analysis. Secret data can be revealed by power analysis attacks such as Simple Power Analysis (...
Thanh-Ha Le, Jessy Clédière, C&eacut...
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
15 years 10 months ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki
CHES
2006
Springer
111views Cryptology» more  CHES 2006»
15 years 10 months ago
Cache-Collision Timing Attacks Against AES
This paper describes several novel timing attacks against the common table-driven software implementation of the AES cipher. We define a general attack strategy using a simplified ...
Joseph Bonneau, Ilya Mironov
CHES
2006
Springer
146views Cryptology» more  CHES 2006»
15 years 10 months ago
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
CHES
2006
Springer
88views Cryptology» more  CHES 2006»
15 years 10 months ago
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Lo...
Zhimin Chen, Yujie Zhou